A Pseudo-Synchronous Skew-Insensitive I/O Scheme for High Band width Memories

Proceedings of 1994 IEEE Symposium on VLSI Circuits Pub Date : 1994-06-09 DOI:10.1109/VLSIC.1994.586203

Sungjoon Kim, Kyeongho Lee, D. Jeong, Yunho Choi

引用次数: 8

Abstract

This paper describes a new skew-insensitive U0 scheme for high bandwidth processor-memory communication, which alleviates the interchip skew problem. High speed transmission up to 770Mbaud was obtained with multiphase clocks generated by phase-locked loop circuit. Interchip skew can be adjusted by the dual loop delay-locked loop based receiver. It is fabricated with 0.9pm CMOS process.

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高带宽存储器的伪同步倾斜不敏感I/O方案

针对高带宽处理器-存储器通信，提出了一种新的不受倾斜影响的U0方案，解决了芯片间的倾斜问题。利用锁相环路产生的多相时钟，实现了770Mbaud的高速传输。双回路延时锁环接收器可调节片间偏斜。采用0.9pm CMOS工艺制造。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1994 IEEE Symposium on VLSI Circuits

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