A Hardware Scheduler for Multicore Block Cipher Processor

Abstract

In consequence of an increasing demand for high-performance system, multiprocessor architectures became trend and used in a variety of fields (e.g. PC, laptops, mobile devices and so on). Multi-core processor can get outstanding throughput with relatively lower operating frequency and power consumption. In order to obtain the maximum throughput in a multi-core structure, it is necessary to schedule assigning tasks to multiple cores. In this paper, we propose a hardware scheduler that is tailored for multicore block cipher and verify the feasibility of the scheduler using AES algorithm.