The Shuffle-Exchange Mesh Topology for 3D NoCs

Abstract

Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of the popular interconnection architectures for multiprocessors due to its scalability and self-routing capability. By vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the shuffle-exchange topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation.