Expressing dynamic reconfiguration by partial evaluation

Abstract

Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment.