Analysis of 8 bit vedic multiplier using different full adder techniques

Abstract

A smart processor’s multipliers remain important to the mathematical computing paradigm. Vedic mathematicians created fundamental multiplication algorithms in ancient times. The Urdhva-Tiryyagbhyam Sutra, an effective Vedic multiplier technique based on 45nm technology, was implemented and designed. Given the importance of multipliers in almost all digital system hardware, building them with high speed, low latency, compact space, and low power consumption would result in successful digital system designs. This is done in 45nm technology with the Cadence Virtuoso tool in FinFET technology. Because of its GDI technique, less hardware, and decreased latency, the implemented Multiplier utilises relatively little power.