GASTIM: A timing analyzer for GaAs digital circuits

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410636

A. Hernández, Luis Gómez, A. Núñez

引用次数: 1

Abstract

A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations.<>

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GASTIM:用于砷化镓数字电路的时序分析仪

提出了一种计算DCFL/SDCFL GaAs电路时延的方法。该模型已在时序分析仪样机中实现。考虑了输入斜率影响和重叠输入转换。仿真结果表明，与HSPICE仿真相比，该模型可以在15%的误差范围内预测出多个电路的延迟时间，并且速度提高了3个数量级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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