Wide operating-range acquisition technique for PLL circuits

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824098

Yi-Cheng Chang, E.W. Greeneich

引用次数: 2

Abstract

A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.

查看原文本刊更多论文

锁相环电路的宽工作范围采集技术

设计了一种采用粗转向技术的宽范围锁相环(PLL)电路，并在MOSIS 1.2 /spl mu/m CMOS技术中实现。整个锁相环电路已经进行了仿真，并且可以在HSPICE上使用3伏电源在160-440 MHz的频率范围内获得锁定。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

自引率

0.00%

发文量