A single ended zero aware asymmetric 4T SRAM cell

Abstract

As SRAM capacity continue to increase to maximize microprocessor performance, power consumption also increases. This paper describes a new 4T SRAM cell that uses zero aware characteristic and single ended bit line and word line in order to achieve low energy consumption in all write and read operations compare to 6T. Design was done using 1.1 V and 45 nm CMOS from PTM. Simulation results showed that the speed of 4T reached 3 and 74 times slower compared to 6T in read and write, respectively. However, the energy consumptions of 4T were at least 37.6 % and 66.4 % smaller compared to write and read energies of 6T respectively.