D. Moran, R. Hill, X. Li, H. Zhou, D. Mclntyre, S. Thoms, R. Droopad, P. Zurcher, K. Rajagopalan, J. Abrokwah, M. Passlack, I. Thayne
{"title":"Sub-micron, metal gate, high-к dielectric, implant-free, enhancement-mode III-V mosfets","authors":"D. Moran, R. Hill, X. Li, H. Zhou, D. Mclntyre, S. Thoms, R. Droopad, P. Zurcher, K. Rajagopalan, J. Abrokwah, M. Passlack, I. Thayne","doi":"10.1109/ESSDERC.2007.4430979","DOIUrl":null,"url":null,"abstract":"The performance of 300 nm, 500 nm and 1 mum metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10 nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-kappa (kappa=20) dielectric stack grown upon a delta-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 mum to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 muA/mum and extrinsic transconductance of 400 muS/mum are obtained from these devices. Gate leakage current of less than 100 pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance sub-micron enhancement mode III-V MOSFETs reported to date.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"164 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
The performance of 300 nm, 500 nm and 1 mum metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10 nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-kappa (kappa=20) dielectric stack grown upon a delta-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 mum to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 muA/mum and extrinsic transconductance of 400 muS/mum are obtained from these devices. Gate leakage current of less than 100 pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance sub-micron enhancement mode III-V MOSFETs reported to date.