Latency Insertion Method for FinFET DC Operating Point Simulation Based on BSIM-CMG

Abstract

As the scaling of planar MOSFETs progresses, various short-channel effects become prominent. The 3-dimensional FinFET was invented to avoid these short-channel effects. Transistor-level simulation with FinFETs is traditionally conducted by SPICE which has super-linear computational complexity. We propose a new method for FinFET DC operating point simulation through the use of the latency insertion method (LIM) which exhibits linear computational complexity. The algorithm incorporates the BSIM-CMG industry-standard compact model. The method is tested on 10 nm and 20 nm FinFETs, and the results are compared with commercial simulators.