A Hardware Architecture for Sample Adaptive Offset Filter in HEVC

Abstract

The newly introduced in-loop filtering tool in the High Efficiency Video Coding (HEVC) standard is the Sample Adaptive Offset (SAO) filter. It mainly helps to reduce the ringing artifacts, that occurs due to distortion or loss of high frequency information. While SAO contributes to a significant increase in coding efficiency, the complexity of in-loop filtering in HEVC encoding is dominated by the estimation of SAO parameters. The SAO estimation primarily includes two phases: the statistics collection phase and the parameter determination phase. The statistics collection phase involves calculating sum and count for band and edge offset. The parameter determination phase involves distortion and offset generation, cost generation and decision, SAO type decision and finally, merge mode decision. In this paper, we designed the SAO encoder’s hardware architecture using a separate clock for each phase. The evaluation of proposed architecture results in decrease in the area of 4%-73% when compared with existing architectures while achieving a similar throughput rate. The design occupies a 70K gate count with a minimum operating frequency of 375MHz.