DESIGN OF SRAM MEMORY USING REVESIBLE AND GDI LOGICS

Abstract

Power consumption is a critical issue in VLSI design. Reversible logic and GDI logic have gained popularity in recent years because to their low power consumption features. These logics have a wide range of uses in upcoming technologies. This logic is critical for the development of low-power structures that are required for the creation of arithmetic circuits used during quantum computing, nanotechnology, and other low-power designs. The GDI method is used to build a variety of reversible logic gates in this paper. A SRAM memory cell has been built utilizing the developed reversible logic gates for improved performance over current designs. Additionally, performance factors like as quantum latency and transistor count are examined for various SRAM designs. Tanner EDA Tools utilizing CMOS 45nm technology are used to simulate the process.