The Eccentrics of CPU FIVR AGS supply noise debug and learnings

Abstract

SoC design, validation, and manufacturing teams all need to work in tandem to ensure a successful product is released to the market. Pre-silicon and post-silicon validation is critical and is performed to ensure minimal Si re-spins at the fabrication and avoid any design bugs reaching the end customer. The post-silicon debug of various power failures issues related to analog supply exhibiting random signatures induced learnings that can help expedite changes in post-Si validation and high-volume screening, Discussed in detail are the debug efforts to identify one of the many Analog Generation Supply (AGS) noise failure and isolation. The paper elucidates reports of the proposed defects and their various bearings, issue root causes, and issue validation suite formation.