ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills

Abstract

A stream compiler (ASC) generates net lists for hardware (FPGA) accelerators from C-like descriptions, obviating the need for hardware skills. The authors present a backend adapter that enables integration of such accelerators with a processor core in the same FPGA. Development of hybrid ASC-accelerated applications using software-only skills is thus made possible, as illustrated by a hybrid power-conscious iDCT implementation