Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Abstract

Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 /spl mu/m 3.3 V CMOS process.