Design, analysis and FPGA implementation LDPC codes with BCH codes

Abstract

In this work, a analysis is performed between LDPC and BCH codes, the BCH codes[1] and LDPC codes both being an error correcting codes that can be used in wireless standards, by implementing these two error correcting codes in FPGA we analyze the Architectures of Error correcting codes in order to show that LDPC is having low area and less power than BCH codes.