Digital fault simulation and test development using JESIM

Abstract

Too often the efforts of digital IC design verification and test are left until after the design has been completed. Sometimes these efforts are not dedicated until after the silicon has been fabricated. The cost, performance, functionality, speed and reliability of the chip are greatly impacted by the lack of proper requirement and preparation for test. This paper discusses the usefulness of the Digital Event and Test simulator "JESIM" for design verification, fault simulation, test vector generation and design for testability.