A fast and accurate characterization method for full-CMOS circuits

Abstract

A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<>