The Future of Test -- Product Integration and its Impact on Test

Abstract

Driving leading edge products with high quality while designs, flows, and processes advance with Moore’s Law will require the semiconductor industry to continue to drive for increasing innovative DFT strategies. The test industry will need to drive for new ideas in the areas of: yield analysis, modeling, test techniques, and defect / fault tolerance. To continue cost effective products while costs escalate, yield analysis will need to take far greater consideration of advanced statistical techniques including consideration of spatial randomness. As UDSM processes become more sensitive to variations in lithography, random particle defects, overlay errors, and printability, it is inevitable that new methods will need to be developed to address the economics of Moore’s Law. At the same time, this convergence will put more demand on design/ circuit techniques as well as the need for advanced yield and process control techniques. IP integration drives intersection of dissimilar IP (EG: low power, high speed, RF, etc) requirements where the need for fault tolerant design will be required to achieve HVM. The key area for new DFT development is analog like methods to accommodate defect tolerance will be required HSIO, integrated RF cores, as well as the introduction of non-conventional fabrication methods are required to meet cost, quality and reliability demands.