A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS

Abstract

Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution. However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worst-case fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL.