On the automatic synthesis of parallel SW from RTL models of hardware IPs

Abstract

Heterogeneous multicore system-on-chips (MPSoCs) provide many degrees of freedom to map functionalities on either SW and HW components. In this scenario, enabling the remapping of HW IPs as SW routines allows to fully exploit the computation power and flexibility provided by heterogeneous MPSoCs. On the other hand, reuse of existent IP cores is the key strategy to explore this large design space in a reasonable amount of time and to reduce the error risk during the MPSoC design flow. A methodology for automatic generation of parallel SW code taking into account these aspects is currently missing. This paper aims at overcoming this limitation, by presenting a methodology to automatically generate parallel SW IPs starting from existent RTL IP models.