A Trace-Driven Validation Methodology for Multi-Processor SOCS

Abstract

Multi-processor systems-on-chip pose a great challenge to validation due to their size and complexity. We approach the problem of MP SoC validation through a tool that uses a reusable scheme to effectively leverage a simulation-based abstraction scheme. Our tool checks an abstract representation of the system across traces obtained by simulating a system level implementation and analyzes the results for correctness. We have effectively used the tool on various live MP SoC design projects.