K. Shibata, Kyoya Takegawa, N. Matsuno, Hisayasu Sato
{"title":"A Low-Voltage −204 dBc/Hz FoMT 1.8-2.7 GHz LC-VCO using 55nm SOTB Technology","authors":"K. Shibata, Kyoya Takegawa, N. Matsuno, Hisayasu Sato","doi":"10.1109/RFIT49453.2020.9226249","DOIUrl":null,"url":null,"abstract":"A low-voltage, low-power, low-phase-noise, and wide-frequency-tuning-range (FTR) LC-VCO for Internet of Things (IoT) has been implemented in the 55nm Silicon on Thin Buried Oxide (SOTB) technology. It uses a tail resistor configuration to reduce phase noise with a low supply voltage of 0.7-0.9 V, where a back-gate bias control of the SOTB technology is also employed. An output amplitude of the LC-VCO is designed so as to minimize frequency sensitivity for both current and supply voltage. These lead to a low phase noise of −101 and −123 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively, with a low power of 0.88 mW. A high-Q LC-tank with low parasitic capacitance design enables a wide FTR of 40.7%, and an excellent figure-of-merit with the FTR (FoMT) of-204 dBc/Hz.","PeriodicalId":283714,"journal":{"name":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT49453.2020.9226249","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A low-voltage, low-power, low-phase-noise, and wide-frequency-tuning-range (FTR) LC-VCO for Internet of Things (IoT) has been implemented in the 55nm Silicon on Thin Buried Oxide (SOTB) technology. It uses a tail resistor configuration to reduce phase noise with a low supply voltage of 0.7-0.9 V, where a back-gate bias control of the SOTB technology is also employed. An output amplitude of the LC-VCO is designed so as to minimize frequency sensitivity for both current and supply voltage. These lead to a low phase noise of −101 and −123 dBc/Hz at 100 kHz and 1 MHz offset frequencies respectively, with a low power of 0.88 mW. A high-Q LC-tank with low parasitic capacitance design enables a wide FTR of 40.7%, and an excellent figure-of-merit with the FTR (FoMT) of-204 dBc/Hz.