A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems

Abstract

Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.