Ultra-low Spike Rate Silicon Neuron

Abstract

We present theory, design and simulation results for a silicon neuron circuit that achieves extremely low spike rates and small footprint by exploiting the low current characteristics in floating gate structures. As in biological counterparts, the spike rate is compressed against stimulant current. Simulations confirm sub-Hertz spike rates in steady state with a stimulant current of 7pA and below, and up to 100x spike rate reduction at InA. With reasonable device variation modelling, Monte Carlo simulation shows that spike rate varies by a standard deviation of 25%.