Synthesis and Consistency Verification of UML Sequence Diagrams with Hierarchical Structure

Abstract

Automatic consistency checking for UML state machine diagrams and sequence diagrams has been expected since developers spend considerable effort to keep the consistency. In particular, the verification of diagrams with a hierarchical structure is required. Although formalization of state machine diagrams with hierarchical structure has been widely treated, it is not yet sufficient for sequence diagrams. In this paper, we propose an automatic method for verifying the consistency between state machine diagrams and sequence diagrams with a hierarchical structure. In our verification framework, the consistency of diagrams is defined as an inclusive relation between the sets of traces and is checked using the FDR model checker. FDR can check refinement relation between processes described as CSPM notation. We provide a process description of state machine diagrams and sequence diagrams and can verify the consistency by checking traces inclusion of processes using FDR. Our description supports for sequence diagrams with a hierarchical structure. We applied the proposed process representation to an example diagram that describes interactions of basic components of a wireless sensor network system and showed that the hierarchical behavior of the diagram could be correctly represented.