A multithreaded HDL simulator for deep submicron SoC designs

Abstract

This work describes a multithreaded, 64-bit, HDL (hardware description language) simulator, V2Sim/spl trade/, which can significantly accelerate the design verification of advanced deep submicron system-on-chip (SoC) circuits by 10/spl times/ or more on any commercial symmetrical multiprocessing (SMP) computers. This work presents the patented, multithreaded simulation algorithm used by V2Sim/spl trade/, and benchmark results of V2Sim/spl trade/ will be depicted to demonstrate the effectiveness of the state-of-the-art algorithm.