Dynamic SEE Testing of Selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs

2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS) Pub Date : 2017-10-01 DOI:10.1109/RADECS.2017.8696210

G. Swift, S. Stone, S. E. García, Kevin W. Wray, W. Rowe, Krysten H. Pfau, Robert Liu, J. Holden, Asa Angeles, Barry L. Willits, Kyle P. Robinson, Andrés Pérez-Celis, M. Wirthlin

引用次数: 5

Abstract

Recent proton and heavy ion SEE data are presented for selected Virtex-7 architectural features requiring dynamic in-beam testing: I/O blocks in various modes, IOSERDES, digital- and phase-locked loop clocks, and block memory’s error correction circuitry.

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Xilinx 28纳米Virtex-7 fpga选定架构特征的动态SEE测试

最近的质子和重离子SEE数据展示了需要动态束流内测试的Virtex-7架构特征:各种模式的I/O块，IOSERDES，数字和锁相环路时钟，以及块存储器的纠错电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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