Impact of technology on low-voltage CMOS and BiCMOS switching delay

Abstract

An alternative switching delay reduction technique for CMOS and BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different V/sub DD/, T/sub ox/, and V/sub T/. PSPICE BiCMOS delay results are presented over a wide range of V/sub DD/, T/sub ox/, and V/sub T/.