Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells

Abstract

We have verified that as the cell transistor width decreases below 100 nm for the NAND flash memory interface trap generation increases rapidly by FN current stress on the tunnel oxide. Accordingly, in contrast to the SILC (Stress-Induced Leakage Current) mechanism for the large dimensional cell transistors, it is revealed that the major failure mechanism of the data retention of 90 nm cell transistors is the relaxation of interface traps, which consist of the fast and slow traps. For the interface trap analysis, a new analysis method using I/sub d/-V/sub g/ hysteresis curve is proposed.