Circuit-Level Safe-Operating-Area of a High-Speed SiGe BiCMOS Wireline Driver

Abstract

In this paper, the circuit-level reliability and device-level reliability mechanisms of a SiGe wireline driver circuit are investigated. The driver is a resistively degenerated and loaded differential cascode amplifier, designed in GlobalFoundries 90-nm SiGe 9HP technology. The goal of this work is to identify a performance-based, circuit-SOA (C-SOA) for a wireline driver in terms of its gain and OP1dB at 5 GHz. This paper presents the concept of performance-based C-SOA as a biasing regime where the RF performance of a circuit does not degrade over time due to applied electrical stress. A wide range of current density, Jc, and collector base voltage, VCB bias points were selected for pre-and post-aging performance assessment. A 10,000 second stress was applied for each bias point to evaluate potential performance degradation. For bias points that saw performance degradation, a device-level explanation is presented. RF circuit performance that saw no degradation was established at 2x JC at peak fT and 1.2x BVCEO, while demonstrating 5 dB of additional (untapped) OP1dB in comparison to the device-specified PDK-provided SOA operating point.