Hardware implementation of cyclic codes error correction on FPGA

Abstract

This paper designs and implements a codec system using the Cyclic code on FPGA. The encoding system was based on the principle of dividing circuits and the decoding system was based on the principle of the Meggitt decoder. This work proposes the look-up table (LUT) method for the decoding system. The implementation results from FPGA show that the proposed decoding method has exactly resulted. In addition, the proposed cyclic decoder core using the look-up table method has lower resource and number of cycles compared to the cyclic decoder core using the Meggitt method.