Implementation of a 64-point FFT on a Multi-Processor System-on-Chip

Abstract

This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6x which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.