FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding

Abstract

Hardware prototyping has been the key to system validation, once the hardware simulation matches the software model results and before the final silicon tape-out. On the other hand, flexible multi-standard implementations are being widely investigated these last years for the challenging channel decoding application. The latest contributions explore ASIP (Application-Specific Instruction-set Processor) concept and target to achieve efficient resource sharing between advanced Turbo and LDPC iterative decoders. In this paper we present an FPGA-based prototype of a multistandard Turbo/LDPC Encoding and Decoding. The functional prototype implements a full communication system including encoder, channel model, ASIP-based decoder and performance counters. All components are flexible and are dynamically configurable through a dedicated GUI (Graphical User Interface). The prototype supports all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.