Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement

Abstract

Detailed routing is one of the most complex and time-consuming stages of VLSI design process. Due to the rapidly growing problem scale and increasing number of design rules in advanced technology nodes, a feasible routing result can only be achieved after many rounds of rip-up and reroute (R&R) iterations, which takes a significantly long runtime. In this paper, we propose several effective and efficient techniques to handle the design rule violations in detailed routing. An adaptive rip-up scheme with two strategies of different effort is designed, which can speed up the R&R phase with comparable solution quality. To cope with the pin access challenge with complex design rule constraints, approaches to refine the pin connections are proposed. Besides, some specific design rules are handled in a post-processing manner efficiently. Experiment result shows that the number of design rule violations can be reduced by 69% with 28% lower runtime on average, after integrating these techniques in Dr. CU 2.0.