Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units

Abstract

Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<>