An implementation of interleaved microstrip motherboard routing in Multi-Gbps I/O channel margin improvement

Abstract

This paper presents an interleaved routing method for motherboard microstrip routing in Multi-Gbps interfaces. The proposed method yields improved channel performance in terms of Eye Height(mV) and Eye Width(ps) margins. Of note is the more prominent improvement in topologies with longer transmission lines. This method enables greater routing flexibility using full microstrip transmission lines with the benefit of improved channel margins at 20 mils inter-pair spacing. More importantly, it allows for the more tightly spaced 15 mils interpair spacing to be utilized without jeopardizing overall channel margins. Ultimately, this translates into a cost saving benefit in line with recent platforms' sleek and thin form factor.