Modeling of Sigma-Delta Modulator Non-idealities with Two Step Quantization in MATLAB/SIMULINK

2011 International Conference on Computational Intelligence and Communication Networks Pub Date : 2011-10-07 DOI:10.1109/CICN.2011.114

S. Jaykar, P. Palsodkar, P. Dakhole

{"title":"Modeling of Sigma-Delta Modulator Non-idealities with Two Step Quantization in MATLAB/SIMULINK","authors":"S. Jaykar, P. Palsodkar, P. Dakhole","doi":"10.1109/CICN.2011.114","DOIUrl":null,"url":null,"abstract":"An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (S?) modulator is proposed. The two-step quantization technique is utilized to design architecture of S? modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing speed. The novel architecture is designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. Switched capacitor (SC) modulator performance is prone to various nonidealities, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC S? modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (noise, finite dc gain, finite bandwidth, slew-rate and saturation voltages). Each nonidealities are modelled mathematically and their behaviour is verified using different analysis in MATLAB Simulink. Simulation results on a second-order SC S? modulator with two step quantization demonstrate the validity of the models proposed.","PeriodicalId":292190,"journal":{"name":"2011 International Conference on Computational Intelligence and Communication Networks","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Computational Intelligence and Communication Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICN.2011.114","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

Abstract

An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (S?) modulator is proposed. The two-step quantization technique is utilized to design architecture of S? modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing speed. The novel architecture is designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. Switched capacitor (SC) modulator performance is prone to various nonidealities, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC S? modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (noise, finite dc gain, finite bandwidth, slew-rate and saturation voltages). Each nonidealities are modelled mathematically and their behaviour is verified using different analysis in MATLAB Simulink. Simulation results on a second-order SC S? modulator with two step quantization demonstrate the validity of the models proposed.

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基于MATLAB/SIMULINK的二步量化Sigma-Delta调制器非理想性建模

提出了一种简化sigma-delta (S?)调制器中模数(A/D)转换器电路实现的结构。采用两步量化技术设计了S?调制器。该架构基于将A/D转换分为两个时间步，以在不降低速度的情况下实现分辨率的提高。该结构具有输入信号高动态范围、高信噪比和高可靠性的特点。开关电容(SC)调制器的性能容易出现各种非理想性，从而影响电路的整体性能。本文提出了一套考虑SC - S?调制器的非理想性，如采样抖动、kT/C噪声和运算放大器参数(噪声、有限直流增益、有限带宽、慢速和饱和电压)。对各非理想性进行了数学建模，并在MATLAB Simulink中通过不同的分析对其行为进行了验证。二阶SC的仿真结果两步量化调制器验证了所提模型的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 International Conference on Computational Intelligence and Communication Networks

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