Design of low-power baseband-processor for RFID tag

Abstract

This paper analyzes the power consumption of an RFID tag and presents a new architecture of a low-power baseband-processor for this special passive tag. The tag consists of a power reception system, an emitter/receiver analog module, an EEPROM and a low-power baseband-processor, compatible with the newest EPCtrade C1G2 UHF RFID protocol. Meanwhile some novel and advanced low-power technologies are adopted for the special low-power baseband-processor, which not only implements the anti-collision schemes and authorization scheme, but also executes read/write operation to EEPROM. The chip was designed and fabricated using 0.35 mum 3 metal layers CMOS technology successfully