Foreground Static Error Calibration for Current Sources Using Backgate Body Biasing

C. Beauquier, D. Duperray, C. Jabbour, P. Desgreys, A. Frappé, A. Kaiser
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引用次数: 0

Abstract

This work presents a detection and calibration circuit for current sources static mismatch introduced by the process of fabrication. The current is corrected through backgate body bias voltage control, which has the benefit of reduced additional parasitic elements, compared to more classic amplitude calibration or sort-and-map solutions. The main application are high speed and high resolution current steering Digital to Analog Converters (DAC). The calibration circuit is applied on a 2 time-interleaved (TI) DAC, with 12 bits of resolution and sampled at a frequency of 16 GHz. Its main requirement is to be able to generate signals up to the Nyquist Band (8 GHz) with Spurious Free Dynamic Range (SFDR) of at least 70 dBFS. We validate the method with a schematic 28 nm FDSOI CMOS transistor level testbench, Montecarlo simulations and temperature variations from 27 °C to 125 °C.
利用后门体偏置标定电流源前景静态误差
本文提出了一种针对制造过程中产生的电流源静态失配的检测和校准电路。电流通过后门体偏置电压控制进行校正,与更经典的幅度校准或排序和映射解决方案相比,其优点是减少了额外的寄生元件。主要应用于高速、高分辨率电流转向数模转换器(DAC)。校准电路应用于2时间交错(TI) DAC,具有12位分辨率,采样频率为16 GHz。其主要要求是能够产生高达奈奎斯特频段(8 GHz)的信号,其无杂散动态范围(SFDR)至少为70 dBFS。我们通过原理图28 nm FDSOI CMOS晶体管电平测试平台,蒙特卡罗模拟和温度变化从27°C到125°C来验证该方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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