Order Reduction by Explicit Moment Matching Based on State Variable Approach

Abstract

The paper presents a sistematic procedure for order reduction needed in an efficient analog large-scale circuit simulation. The procedure uses a reduced number of the original circuit moments to obtain an accurate approximation of the circuit function corresponding to an equivalent reduced-size circuit. An efficient program for state equation formulation and transfer function generation allow the computation of the original circuit moments. Some examples are done to illustrate the method.