Current Crowding and Stress Effects in WCSP Solder Interconnects: A Simulative and Practical Study about the Effects of Major Electromigration Failure Mechanisms in DC and Pulsed-DC Conditions

Allison T. Osmanson, Y. Kim, H. Madanipour, Mohsen Tajedini, C. Kim, P. Thompson, Q. Cherr, L. Nguyen
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Abstract

Electromigration (EM) induced failure is inevitable in wafer-level chip scale package microelectronic packages (WCSP), especially with the implementation of lead-free solders. Many factors contribute to EM failure such as joule heating and current crowding. EM can induce void formation, which can eventually lead to open-circuit failure. Due to its nature, EM is a critical failure concern to the microelectronic industry and can be influenced by current conditions. This study examines the failure mechanisms in solder joints implemented in WCSP packages in Direct Current (DC) and DC-pulse current conditions with varying Duty Factors (DF). DF represents the on-off time for DC to flow through the device under test (DUT). Further, a transient simulative study using finite element method (FEM) explores the failure mechanism and investigates the stress development with DC and DF conditions. Findings suggested that a lower duty factor yielded longer time to failure (TTF). Meanwhile, higher pulsed DC DF yielded a lower TTF than DC. This study aims to explain the failure mechanism with each DF. This study aims to explain this phenomenon and suggests the need for further exploration.
WCSP焊料互连中的电流拥挤和应力效应:直流和脉冲直流条件下主要电迁移失效机制影响的模拟和实际研究
在晶圆级芯片级封装微电子封装(WCSP)中,电迁移(EM)诱发的失效是不可避免的,特别是随着无铅焊料的实施。许多因素导致电磁失效,如焦耳加热和电流拥挤。电磁可诱发空穴形成,最终导致开路失效。由于其性质,电磁是微电子工业的一个关键故障问题,并可能受到当前条件的影响。本研究考察了WCSP封装中焊点在直流(DC)和直流脉冲电流条件下的失效机制,这些条件具有不同的占空比(DF)。DF表示直流流过被测设备(DUT)的通断时间。在此基础上,利用有限元方法进行了瞬态模拟研究,探讨了破坏机制,并研究了直流和DF条件下的应力发展情况。研究结果表明,较低的占空因子产生较长的失效时间(TTF)。同时,较高的脉冲直流DF产生较低的TTF。本研究旨在解释每个DF的失效机制。本研究旨在解释这一现象,并提出进一步探索的必要性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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