A 2000 Gate Bipolar Uncommitted Logic Array

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468739

S. Colaco, H. Hulmes

引用次数: 0

Abstract

A 2000 gate high speed Bipolar Uncommitted Logic Array using 3 micrometer minimum feature sizes has been described, The chip comprises 1980 CML gates and 64 I/O cells. Typical gate delay is 6 nanoseconds. Power Delay time produced is 0.5 pJ. A single 5 volt supply powers the chip which is fully T.T.L. compatible.

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2000门双极未提交逻辑阵列

描述了一种最小特征尺寸为3微米的2000门高速双极未提交逻辑阵列，该芯片由1980个CML门和64个I/O单元组成。典型的门延迟为6纳秒。产生的功率延迟时间为0.5 pJ。单个5伏电源为芯片供电，完全兼容t.t.l。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

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