Design of a low power 54/spl times/54 bit multiplier based on an intelligent window detector

Abstract

In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.