Parity error detection in embedded computer system

Abstract

This paper considers the problem of implementing parity error detection in a bus transceiver circuit used in highly-reliable embedded computer systems. The design of a 32-bit bus transceiver is efficient when either capacitive load/coupling between bus lines causes transitions or signal delays on such lines with respect to the fault-free case, or when permanent faults (stuck at zero/one) on bus lines exist. Transient errors are detected by self-testing checking hardware, while permanent faults are sensed by boundary scan logic. The transceiver features high-speed online detection and can be implemented using custom and semi-custom VLSI ICs, very deep submicron technology, as well as low-cost FPGAs.