Modelling the saturation region of power bipolar mode JFET for SPICE simulation

Abstract

A circuit model of a power bipolar JFET (junction field-effect transistor) which is able to describe accurately the saturation region of the device both in static and in switching operations is presented. The model permits a good estimate of the device conduction losses and of the device storage time. The equivalent circuit was totally developed on a physical basis, and the extraction of the model parameters can be directly computed from geometrical and physical parameters of the device. The model accurately describes experimental device characteristics and is used to get an insight into the physics of the switching operation of the bipolar JFET in the case of an inductive load.<>