Scaleable shadow stack for a configurable DSP concept

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings. Pub Date : 2003-07-22 DOI:10.1109/IWSOC.2003.1213039

C. Panis, Raimund Leitner, J. Nurmi

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引用次数: 3

Abstract

SoC (System-on-Chip) applications map complex system functions on a single die. The increasing importance of flexibility in SoC applications leads to raising portion implemented in firmware. Therefore, the demand on computational power of the embedded processors in the application is increasing. The newest silicon technologies (e.g. 0.13 /spl mu/m and lower) help to increase the reachable frequency, but the demand cannot be sufficiently satisfied. One approach to increase the processor frequency is the introduction of pipelining. To guarantee data consistency in deep pipelined processors different methods have been developed. Additional complexity is introduced by the occurrence of interrupts. This paper describes a concept to enable data consistency between the instructions of different pipeline stages in pipelined DSP kernels during interrupt service routines, without the interaction of the DSP itself and with no restrictions concerning the nesting level of the interrupts. The scaleable shadow stack is part of a development project for a configurable DSP concept.

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可扩展的阴影堆栈为一个可配置的DSP概念

SoC(片上系统)应用程序将复杂的系统功能映射到单个芯片上。SoC应用中灵活性的重要性日益增加，导致固件中实现的部分增加。因此，在应用中对嵌入式处理器的计算能力要求越来越高。最新的硅技术(如0.13 /spl mu/m及以下)有助于提高可达频率，但不能充分满足需求。提高处理器频率的一种方法是引入流水线。为了保证深度流水线处理器中的数据一致性，人们开发了不同的方法。中断的出现带来了额外的复杂性。本文描述了在中断服务例程期间，在流水线DSP内核中不同管道阶段指令之间实现数据一致性的概念，而不需要DSP本身的交互，也不需要对中断的嵌套级别进行限制。可缩放的影子堆栈是可配置DSP概念开发项目的一部分。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.

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