A novel low-voltage low-power 5.8 GHz CMOS down-conversion mixer design

Abstract

This paper presents a 5.8 GHz low voltage and low power down-conversion mixer design integrated in a TSMC 0.18 /spl mu/m CMOS process. The proposed method features that an RF input stage converts the RF input voltage to current, which is coupled to the core of Gilbert Cell using current source transistor at bottom and furthermore reduces the supply voltage. The LO frequency is at 5.6 GHz. The designed mixer requires only a 1.5 V supply voltage and consumes 6.89 mW DC power. At 5.8 GHz, this mixer has single-sideband noise figure (SSB NF) of 14.3 dB, with input return loss of -18.6 dB, third-order input intercept point (IIP3) of -2.94 dBm, and conversion gain of 7 dB.