Layout engineering to suppress hysteresis of negative capacitance FinFET

Abstract

Negative capacitance (NC), which arises from two energy minima of ferroelectric material, is proposed as one of the solutions for the next generation CMOS technology. However, the side-effect (i.e., hysteresis in current-vs.-voltage characteristic) of NC FinFET should be minimized, especially for being adopted as CMOS logic devices. If the capacitance matching between the ferroelectric capacitor and the dielectric capacitor in NC FinFET is satisfied, hysteresis-free and steep switching features can be obtained. In this work, the hysteresis in current-vs.-voltage characteristic is suppressed by lowering the capacitance value of FinFET (i.e., using the layout engineering for FinFET): While the hysteresis of NC FinFET was decreased, the performance degradation was negligible.