LNA circuit design counting the interconnect line parasitics

Abstract

This paper, presents a 24GHz Amplifier circuit demonstrator designed and fabricated in 0.25μm BiCMOS mature technology from NXP Semiconductors in order to evaluate the effect of the interconnect lines on impedance matching. It features 11 dB of gain, 7.6 dB of noise figure (NF) at the working frequency. The input/output impedances are matched close to 50 Ohm with an input return loss of-12 dB and output return loss of about -13 dB. The matching methodology is improved by considering the interconnect lines (from the Layout view) in the matching networks. Schematic circuit simulations and measurements are used to evaluate the amplifier circuit performances. The results are presented here and show a good agreement between both, measurements and simulations.